Leakage Current Calibration Procedures of Amorphous Silicon Thin-Film Transistors

Figure 1. (a) Trap occupancy of a trapping level under non-equilibrium conditions (b) probability of occupation (c) conceptual diagram of DOS, probability of occupation, and ionized densities in the a-Si TFTs. Figure 2. Examples of ATLAS simulation results with DEFECT and SAVE TRAP.FILE statements. Introduction Amorphous silicon Thin-Film Transistors (a-Si TFTs) are widely used as the switching device of liquid crystal display (LCD) technology. For development and analysis of a-Si TFTs, many research groups are trying to understand the physical mechanisms of a-Si TFTs. In particular, leakage current behavior is a major consideration for switching devices like a-Si TFTs. To analyze the leakage current mechanisms, calibration with numerical simulation is required.